eprintid: 4044
rev_number: 9
eprint_status: archive
userid: 375
dir: disk0/00/00/40/44
datestamp: 2020-08-02 06:21:45
lastmod: 2020-08-02 06:21:45
status_changed: 2020-08-02 06:21:45
type: patent
metadata_visibility: show
creators_name: Abdallah, Abderazek Ben
creators_name: Dang, Nam Khanh
creators_name: Hisada, Masayuki
creators_id: benab@u-aizu.ac.jp
creators_id: dnk0904@gmail.com
corp_creators: University of Aizu
corp_creators: VNU University of Engineering
corp_creators: Aizu Laboratory Inc
title: ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置
TSV Error Tolerant Router Device for 3D Network On Chip
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
divisions: lab_sis
abstract: A TSV error tolerant router device for 3D network-on-chip is disclosed. In a TSV error tolerant router device for a 3D network-on-chip having a plurality of routers arranged in each of a plurality of layers, and routers between the layers are connected by through-silicon vias, the through-silicon vias are provided. Each of which belongs to one corresponding router, has a plurality of clusters around the corresponding router, and is adjacent to the corresponding router when one of the plurality of clusters belonging to the corresponding router is defective A router is selected, and one cluster of the selected router is replaced in place of the defective cluster, maintaining connectivity between the layers. [Selection] Figure 2
date: 2019-06-13
date_type: submitted
official_url: https://patents.google.com/patent/JP2019092020A/en
id_number: JP2019092020A
full_text_status: public
pages: 13
patent_applicant: Univ of Aizu, Aizu Laboratory Inc
citation:   Univ of Aizu, Aizu Laboratory Inc  (2019) ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置 TSV Error Tolerant Router Device for 3D Network On Chip.  JP2019092020A.   
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/4044/1/JP2019092020A.pdf