eprintid: 4049
rev_number: 14
eprint_status: archive
userid: 375
dir: disk0/00/00/40/49
datestamp: 2020-09-07 08:16:54
lastmod: 2020-11-29 02:17:19
status_changed: 2020-09-07 08:16:54
type: article
metadata_visibility: show
creators_name: Dang, Nam Khanh
creators_name: Ahmed, Akram Ben
creators_name: Abdallah, Abderazek Ben
creators_name: Tran, Xuan Tu
creators_id: dnk0904@gmail.com
creators_id: benab@u-aizu.ac.jp
creators_id: tutx@vnu.edu.vn
title: A thermal-aware on-line fault tolerance method for TSV lifetime reliability in 3D-NoC systems
ispublished: pub
subjects: Communications
subjects: ECE
subjects: ElectronicsandComputerEngineering
subjects: IT
subjects: Scopus
subjects: isi
divisions: lab_sis
abstract: Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, $R$ redundant TSVs can fully localize and correct $R$ defects and support the detection of $R+1$ defects. 	Moreover, by using $G$ groups, it can localize up to GxR and detect up to Gx(R+1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50\% localization). 
By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.
date: 2020-09
date_type: published
publisher: IEEE
official_url: https://ieeexplore.ieee.org/document/9189765
id_number: 10.1109/ACCESS.2020.3022904
full_text_status: restricted
publication: IEEE Access
volume: 8
pagerange: 166642-166657
refereed: TRUE
issn: 2169-3536
citation:   Dang, Nam Khanh and Ahmed, Akram Ben and Abdallah, Abderazek Ben and Tran, Xuan Tu  (2020) A thermal-aware on-line fault tolerance method for TSV lifetime reliability in 3D-NoC systems.  IEEE Access, 8 .   pp. 166642-166657.  ISSN 2169-3536     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/4049/1/FINAL%20Article.pdf