@inproceedings{SisLab421,
       booktitle = {The 17th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems},
           month = {April},
           title = {An Efficient Hardware Architecture for Inter-Prediction in H. 264/AVC Encoders},
          author = {Nam Khanh Dang and Xuan Tu Tran and Alain Merigot},
            year = {2014},
           pages = {294--297},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/421/},
        abstract = {In this paper, we propose a design methodology for the inter-prediction in H.264/AVC codecs by addressing the relationship between its main processes. The target of this methodology is to optimize the design in order to get better performance while keeping a reasonable design cost. An efficient hardware architecture for the inter-prediction in H.264/AVC codecs is then proposed with three key techniques: a modified full search algorithm with bandwidth efficiency, pipelining technique, and data reuse strategy. With this approach, the inter-prediction has been successfully designed and implemented with a CMOS 180nm technology which provides low cost in terms of latency, hardware overhead and memory bandwidth. The design is initially targeted to CIF video format; however, it is obviously suitable for real-time HD 1080p video format.}
}