TY  - CONF
ID  - SisLab421
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/421/
A1  - Dang, Nam Khanh
A1  - Tran, Xuan Tu
A1  - Merigot, Alain
Y1  - 2014/04/23/
N2  - In this paper, we propose a design methodology for the inter-prediction in H.264/AVC codecs by addressing the relationship between its main processes. The target of this methodology is to optimize the design in order to get better performance while keeping a reasonable design cost. An efficient hardware architecture for the inter-prediction in H.264/AVC codecs is then proposed with three key techniques: a modified full search algorithm with bandwidth efficiency, pipelining technique, and data reuse strategy. With this approach, the inter-prediction has been successfully designed and implemented with a CMOS 180nm technology which provides low cost in terms of latency, hardware overhead and memory bandwidth. The design is initially targeted to CIF video format; however, it is obviously suitable for real-time HD 1080p video format.
TI  - An Efficient Hardware Architecture for Inter-Prediction in H. 264/AVC Encoders
SP  - 294
M2  - Warsaw, Poland
AV  - restricted
EP  - 297
T2  - The 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
ER  -