eprintid: 4243
rev_number: 9
eprint_status: archive
userid: 4
dir: disk0/00/00/42/43
datestamp: 2020-12-11 03:25:23
lastmod: 2020-12-11 03:25:23
status_changed: 2020-12-11 03:25:23
type: conference_item
metadata_visibility: show
creators_name: Dong, Pham Khoi
creators_name: Nguyen, Kiem Hung
creators_name: Hoang, Van Phuc
creators_name: Tran, Xuan Tu
creators_id: kiemhung@vnu.edu.vn
creators_id: phuchv@mta.edu.vn
creators_id: tutx@vnu.edu.vn
title: Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
subjects: isi_scopus_conf
divisions: fac_fet
divisions: lab_sis
abstract: Nowadays, the Internet of Things (IoT) has been a focus of research that improves and optimizes our daily life based on intelligent sensors and smart objects working together. Thanks to Internet Protocol connectivity, devices can be connected to the Internet, thus allowing them to be read, controlled, and managed at any time and at any place. Security and privacy are the key issues for deploying IoT applications, and still face some enormous challenges; especially, for devices that require high throughput and low latency as IoT cameras, IoT gateways, high-quality video conferencing systems… In this paper, we proposed a 10-cores AES hardware architecture to achieve high throughput. These cores shared KeyExpansion Block so this architecture has high efficiency in term of area and power consumption. Fully parallel, outer round pipeline technique is also used to achieve low latency. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. On the other hand, clock gating technique is used to save power consumption. We use PrimeTime tool (Synopsys) to estimate the power consumption. Implementation results show that the proposed architecture achieves a throughput of 853.8 Gbps at the maximum operating frequency of 667 MHz and clock gating technique allows more power savings.
date: 2020-12-08
date_type: published
official_url: https://apccas2020.org/
contact_email: tutx@vnu.edu.vn
full_text_status: public
pres_type: paper
pagerange: 72-75
event_title: 2020 16th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)
event_location: Ha Long Bay, Vietnam
event_dates: 8-10 December 2020
event_type: conference
refereed: TRUE
projects: KC.01.21/16-20
citation:   Dong, Pham Khoi and Nguyen, Kiem Hung and Hoang, Van Phuc and Tran, Xuan Tu  (2020) Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture.  In: 2020 16th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 8-10 December 2020, Ha Long Bay, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/4243/1/a19-khoi_dong.pdf