eprintid: 4244
rev_number: 9
eprint_status: archive
userid: 4
dir: disk0/00/00/42/44
datestamp: 2020-12-11 03:30:07
lastmod: 2020-12-11 03:30:07
status_changed: 2020-12-11 03:30:07
type: conference_item
metadata_visibility: show
creators_name: Nguyen, Duy Anh
creators_name: Tran, Xuan Tu
creators_name: Dang, Nam Khanh
creators_name: Iacopi, Francesca
creators_id: danguyen@vnu.edu.vn
creators_id: tutx@vnu.edu.vn
creators_id: khanh.n.dang@vnu.edu.vn
creators_id: Francesca.Iacopi@uts.edu.au
title: A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
subjects: isi_scopus_conf
divisions: fac_fet
divisions: lab_sis
abstract: The training of Deep Spiking Neural Networks (DSNNs) is facing many challenges due to the non-differentiable nature of spikes. The conversion of a traditional Deep Neural Networks (DNNs) to its DSNNs counterpart is currently one of the prominent solutions, as it leverages many state-of-the-art pre-trained models and training techniques. However, the conversion of max-pooling layer is a non-trivia task. The state-of-the-art conversion methods either replace the max-pooling layer with other pooling mechanisms or use a max-pooling method based on the cumulative number of output spikes. This incurs both memory storage overhead and increases computational complexity, as one inference in DSNNs requires many timesteps, and the number of output spikes after each layer needs to be accumulated. In this paper, we propose a novel max-pooling mechanism that is not based on the number of output spikes but is based on the membrane potential of the spiking neurons. Simulation results show that our approach still preserves classification accuracies on MNIST and CIFAR10 dataset. Hardware implementation results show that our proposed hardware block is lightweight with an area cost of 15.3k Gate Equivalent, at a maximum frequency of 300 MHz.
date: 2020-12-08
date_type: published
official_url: https://apccas2020.org/
contact_email: tutx@vnu.edu.vn
full_text_status: restricted
pres_type: paper
pagerange: 226-229
event_title: 2020 16th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS)
event_location: Ha Long Bay, Vietnam
event_dates: 8-10 December 2020
event_type: conference
refereed: TRUE
funders: TXTCN.20.01
citation:   Nguyen, Duy Anh and Tran, Xuan Tu and Dang, Nam Khanh and Iacopi, Francesca  (2020) A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks.  In: 2020 16th IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), 8-10 December 2020, Ha Long Bay, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/4244/1/a58-nguyen.pdf