%A Kiem Hung Nguyen
%A Quang Vinh Tran
%A Xuan Tu Tran
%T Data Locality Exploitation for Coarse-grained Reconfigurable Architecture in Reconfigurable Network-on-Chips
%X This paper proposes a Coarse-grained Reconfigurable Architecture (CGRA) applied to the multimedia processing and communications processing. To solve the huge bandwidth requirement of parallel processing arrays, the proposed CGRA architecture focuses on the exploitation of data locality to reduce data access bandwidth and increase efficiency of pipelined execution of the kernel loops. The proposed architecture has been modeled using both C and VHDL language aiming at simulating and analyzing various parameters of the target architecture, as well as supporting hardware/software co-verification when mapping applications onto the target system. Some benchmark applications have been mapped onto the models of the CGRA in order to prove the high flexibility and performance of the architecture that is suitable for a wide range of multimedia and communications processing applications. The proposed CGRA can be applied as computing resources in reconfigurable Network-on-Chips.
%C Hanoi, Vietnam
%D 2014
%P 75-81
%L SisLab432