@article{SisLab46,
          volume = {44},
          number = {4},
           month = {April},
          author = {Edith Beigne and Clermidy Fabien and H{\'e}l{\`e}ne Lhermet and Sylvain Miermont and Yvain Thonnart and Xuan Tu Tran and Alexandre Valentian and Didier Varreau and Pascal Vivet and Xavier Popon and Hugo Lebreton},
           title = {An Asynchronous Power Aware and Adaptive NoC Based Circuit},
            year = {2009},
         journal = {IEEE Journal of Solid State Circuits (JSSC)},
             doi = {10.1109/JSSC.2009.2014206},
           pages = {1167--1177},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/46/},
        abstract = {In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an
issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an
asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.}
}