relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/46/
title: An Asynchronous Power Aware and Adaptive NoC Based Circuit
creator: Beigne, Edith
creator: Fabien, Clermidy
creator: Lhermet, Hélène
creator: Miermont, Sylvain
creator: Thonnart, Yvain
creator: Tran, Xuan Tu
creator: Valentian, Alexandre
creator: Varreau, Didier
creator: Vivet, Pascal
creator: Popon, Xavier
creator: Lebreton, Hugo
subject: Electronics and Communications
subject: Electronics and Computer Engineering
subject: ISI-indexed journals
description: In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an  issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an  asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.
date: 2009-04-01
type: Article
type: PeerReviewed
format: application/pdf
language: en
identifier: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/46/1/JSSC2009-An_Asynchronous_Power_Aware_and_Adaptive_NoC_Based_Circuit.pdf
identifier:   Beigne, Edith and Fabien, Clermidy and Lhermet, Hélène and Miermont, Sylvain and Thonnart, Yvain and Tran, Xuan Tu and Valentian, Alexandre and Varreau, Didier and Vivet, Pascal and Popon, Xavier and Lebreton, Hugo  (2009) An Asynchronous Power Aware and Adaptive NoC Based Circuit.  IEEE Journal of Solid State Circuits (JSSC), 44  (4).   pp. 1167-1177.      
relation: 10.1109/JSSC.2009.2014206