TY  - JOUR
ID  - SisLab46
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/46/
IS  - 4
A1  - Beigne, Edith
A1  - Fabien, Clermidy
A1  - Lhermet, Hélène
A1  - Miermont, Sylvain
A1  - Thonnart, Yvain
A1  - Tran, Xuan Tu
A1  - Valentian, Alexandre
A1  - Varreau, Didier
A1  - Vivet, Pascal
A1  - Popon, Xavier
A1  - Lebreton, Hugo
Y1  - 2009/04/01/
N2  - In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an
issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an
asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.
JF  - IEEE Journal of Solid State Circuits (JSSC)
VL  - 44
TI  - An Asynchronous Power Aware and Adaptive NoC Based Circuit
SP  - 1167
AV  - public
EP  - 1177
ER  -