eprintid: 46
rev_number: 16
eprint_status: archive
userid: 4
dir: disk0/00/00/00/46
datestamp: 2012-11-02 04:05:22
lastmod: 2017-01-17 02:18:07
status_changed: 2012-11-02 04:05:22
type: article
metadata_visibility: show
creators_name: Beigne, Edith
creators_name: Fabien, Clermidy
creators_name: Lhermet, Hélène
creators_name: Miermont, Sylvain
creators_name: Thonnart, Yvain
creators_name: Tran, Xuan Tu
creators_name: Valentian, Alexandre
creators_name: Varreau, Didier
creators_name: Vivet, Pascal
creators_name: Popon, Xavier
creators_name: Lebreton, Hugo
creators_id: tutx@vnu.edu.vn
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: VNU-UET
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: CEA-LETI
corp_creators: CEA-LETI
title: An Asynchronous Power Aware and Adaptive NoC Based Circuit
ispublished: pub
subjects: ECE
subjects: ElectronicsandComputerEngineering
subjects: isi
divisions: fac_fet
divisions: lab_sis
abstract: In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an
issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an
asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.
date: 2009-04-01
date_type: published
id_number: 10.1109/JSSC.2009.2014206
full_text_status: public
publication: IEEE Journal of Solid State Circuits (JSSC)
volume: 44
number: 4
pagerange: 1167-1177
refereed: TRUE
related_url_url: http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CCUQFjAA&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D4804962&ei=oUeTUN6VHMuYiAeexIBg&usg=AFQjCNG9T-XgcODyUoYXXWUz1Iiqm6z75w
related_url_type: pub
citation:   Beigne, Edith and Fabien, Clermidy and Lhermet, Hélène and Miermont, Sylvain and Thonnart, Yvain and Tran, Xuan Tu and Valentian, Alexandre and Varreau, Didier and Vivet, Pascal and Popon, Xavier and Lebreton, Hugo  (2009) An Asynchronous Power Aware and Adaptive NoC Based Circuit.  IEEE Journal of Solid State Circuits (JSSC), 44  (4).   pp. 1167-1177.      
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/46/1/JSSC2009-An_Asynchronous_Power_Aware_and_Adaptive_NoC_Based_Circuit.pdf