@inproceedings{SisLab47,
       booktitle = {The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011)},
           month = {August},
           title = {Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder},
          author = {Duy Hieu Bui and Xuan Tu Tran},
            year = {2011},
           pages = {33--37},
            note = {ISBN: 978-4-88552-258-1},
        keywords = {SystemC, VHDL, co-design, co-simulation, JPEG encoder},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/47/},
        abstract = {Nowadays, System-on-Chip (SoC) systems are becoming more and more complex and need more time to model, simulate and verification. To reduce the complexity of the system and to boost development time, a new design methodology is required. Along with SystemC library, multi-level abstraction design methodology is proposed as the key concept in SoC design. In this paper, the authors apply this methodology to model and simulate a JPEG encoder using the combination of SystemC and VHDL to explore the architecture and implement the design into hardware components. Consequently, some parts of the JPEG encoder has successfully synthesized and implemented using FPGA tools. In conclusion, the design methodology gives designers a fast way and step-by-step to explore the hardware architecture, simulate and implement the system.}
}