eprintid: 47
rev_number: 11
eprint_status: archive
userid: 4
dir: disk0/00/00/00/47
datestamp: 2012-11-02 06:06:39
lastmod: 2017-01-17 02:36:06
status_changed: 2012-11-02 06:06:39
type: conference_item
metadata_visibility: show
creators_name: Bui, Duy Hieu
creators_name: Tran, Xuan Tu
creators_id: hieubd@vnu.edu.vn
creators_id: tutx@vnu.edu.vn
corp_creators: VNU-UET
corp_creators: VNU-UET
title: Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder
ispublished: pub
subjects: ECE
subjects: Electronics
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
keywords: SystemC, VHDL, co-design, co-simulation, JPEG encoder
note: ISBN: 978-4-88552-258-1
abstract: Nowadays, System-on-Chip (SoC) systems are becoming more and more complex and need more time to model, simulate and verification. To reduce the complexity of the system and to boost development time, a new design methodology is required. Along with SystemC library, multi-level abstraction design methodology is proposed as the key concept in SoC design. In this paper, the authors apply this methodology to model and simulate a JPEG encoder using the combination of SystemC and VHDL to explore the architecture and implement the design into hardware components. Consequently, some parts of the JPEG encoder has successfully synthesized and implemented using FPGA tools. In conclusion, the design methodology gives designers a fast way and step-by-step to explore the hardware architecture, simulate and implement the system.
date: 2011-08-08
date_type: published
full_text_status: public
pres_type: paper
pagerange: 33-37
event_title: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011)
event_location: Hanoi, Vietnam
event_dates: 8-10 August 2011
event_type: conference
refereed: TRUE
projects: QGDA.10.02
citation:   Bui, Duy Hieu and Tran, Xuan Tu  (2011) Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder.  In: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), 8-10 August 2011, Hanoi, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/47/1/JPEG_SYSTEMC_VHDL_icdv2011_full_pp_FINAL.pdf