@inproceedings{SisLab48,
       booktitle = {The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011)},
           month = {August},
           title = {FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture},
          author = {Nam Khanh Dang and Van Thanh Vu Le and Xuan Tu Tran},
            year = {2011},
           pages = {112--116},
            note = {ISBN: 978-4-88552-258-1},
        keywords = {Network-on-Chip},
             url = {https://eprints.uet.vnu.edu.vn/eprints/id/eprint/48/},
        abstract = {The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows.}
}