relation: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/48/
title: FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture
creator: Dang, Nam Khanh
creator: Le, Van Thanh Vu
creator: Tran, Xuan Tu
subject: Electronics and Communications
subject: Electronics and Computer Engineering
description: The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows.
date: 2011-08-08
type: Conference or Workshop Item
type: PeerReviewed
format: application/pdf
language: en
identifier: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/48/1/IEICE2011%20normal%20router%20for%20NoCs%20-%2010-FINAL.pdf
identifier:   Dang, Nam Khanh and Le, Van Thanh Vu and Tran, Xuan Tu  (2011) FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture.  In: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), 8-10 August 2011, Hanoi, Vietnam.