TY  - CONF
N1  - ISBN: 978-4-88552-258-1
ID  - SisLab48
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/48/
A1  - Dang, Nam Khanh
A1  - Le, Van Thanh Vu
A1  - Tran, Xuan Tu
Y1  - 2011/08/08/
N2  - The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows.
KW  - Network-on-Chip
TI  - FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture
SP  - 112
M2  - Hanoi, Vietnam
AV  - public
EP  - 116
T2  - The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011)
ER  -