%A Nam Khanh Dang
%A Van Thanh Vu Le
%A Xuan Tu Tran
%O ISBN: 978-4-88552-258-1
%T FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture
%X The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows.
%K Network-on-Chip
%P 112-116
%D 2011
%C Hanoi, Vietnam
%L SisLab48