eprintid: 49
rev_number: 10
eprint_status: archive
userid: 4
dir: disk0/00/00/00/49
datestamp: 2012-11-02 06:14:37
lastmod: 2017-01-17 02:36:21
status_changed: 2012-11-02 06:14:37
type: conference_item
metadata_visibility: show
creators_name: Tran, Xuan Tu
creators_id: tutx@vnu.edu.vn
corp_creators: VNU-UET
title: Network-on-Chips: Design and Test Challenges in Nanoscale Era
ispublished: pub
subjects: ECE
subjects: Electronics
subjects: ElectronicsandComputerEngineering
divisions: fac_fet
divisions: lab_sis
keywords: SystemC, VHDL, co-design, co-simulation, JPEG encoder
note: ISBN: 978-4-88552-258-1
abstract: Nowadays, more and more complex intellectual property (IP) cores communicating with each other has been intently integrated into a system to meet the high demand of new applications. This make the on-chip communication become a critical issue and the conventional bus based communication using a single bus or a hierarchy of busses could not response to the communication requirements between the integrated IP cores because of their poor scalability with system size, their shared bandwidth between all the integrated IPs, and the energy efficiency requirements of final products. 
To overcome those problems, the Network-on-Chip (NoC) paradigm has been proposed as a promising on-chip communication solution for designing complex systems, especially when the semiconductor technology turns into nanoscale era. However, the development of design and test methodologies for this new paradigm is a complicated and time consuming engineering process, concerning to not only hardware design issues but also network protocols matters. After a decade of research and development, the NoC designers still have to face many challenges to bring the paradigm to final industrial products. 
This talk will first give a brief introduction to the network-on-chip concept, and then addresses on main challenges in de-signing and testing the on-chip communication network well as the attached IP cores. A practical example of designing and testing a network on chip will be also presented to illustrate the mentioned challenges.
date: 2011-08-08
date_type: published
full_text_status: public
pres_type: keynote
pagerange: 111-111
event_title: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011)
event_location: Hanoi, Vietnam
event_dates: 8-10 August 2011
event_type: conference
refereed: TRUE
citation:   Tran, Xuan Tu  (2011) Network-on-Chips: Design and Test Challenges in Nanoscale Era.  In: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), 8-10 August 2011, Hanoi, Vietnam.     
document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/49/1/ICDV%202011%20invited%20paper%20with%20ToC.pdf