TY  - CONF
N1  - ISBN: 978-1-61284-459-6
ID  - SisLab50
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/50/
A1  - Tran, Van Huan
A1  - Tran, Xuan Tu
Y1  - 2011/04//
N2  - In this paper, we present the design and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The design is compatible with PLB bus and has a high potential to be used in Xilinx FPGA-based systems. The ability to provide multiple display resolutions (up to WXGA 1280x800) and a customizable internal FIFO make the proposed architecture suitable for several FPGA devices. Furthermore, we have also offered a useful software library to enable the text mode feature. These highlight features have been validated through the demonstration of an application.
TI  - An Efficient Architecture Design for VGA Monitor Controller
SP  - 3917
M2  - Hubei, China
AV  - public
EP  - 3921
T2  - The International Conference on Consumer Electronics, Communications and Networks (IEEE CECNet 2011)
ER  -