eprintid: 51 rev_number: 10 eprint_status: archive userid: 4 dir: disk0/00/00/00/51 datestamp: 2012-11-02 06:24:48 lastmod: 2017-01-17 02:36:40 status_changed: 2012-11-02 06:24:48 type: conference_item metadata_visibility: show creators_name: Tran, Xuan Tu creators_name: Tran, Van Huan creators_id: tutx@vnu.edu.vn creators_id: huantv@vnu.edu.vn corp_creators: VNU-UET title: Cost-Efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC Encoders ispublished: pub subjects: ECE subjects: Electronics subjects: ElectronicsandComputerEngineering divisions: fac_fet divisions: lab_sis abstract: In this paper, we present a low cost Forward Transform and Quantization (FTQ) implementation for H.264/AVC encoders in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755um2 (approximate 15KGates), with the 130nm TSMC CMOS technology. date: 2011-04-13 date_type: published full_text_status: public pres_type: paper pagerange: 47-52 event_title: The IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS) event_location: Cottbus, Germany event_dates: 13-15 April 2011 event_type: conference refereed: TRUE citation: Tran, Xuan Tu and Tran, Van Huan (2011) Cost-Efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC Encoders. In: The IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS), 13-15 April 2011, Cottbus, Germany. document_url: https://eprints.uet.vnu.edu.vn/eprints/id/eprint/51/1/PID1711113.pdf