TY  - CONF
ID  - SisLab54
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/54/
A1  - Tran, Van Huan
A1  - Nguyen, Ngoc Mai
A1  - Nguyen, Van Mien
A1  - Tran, Xuan Tu
Y1  - 2010/06/01/
N2  - This paper presents a low-cost and high-performance
hardware design of forward transform and quantization (FTQ)
for an H.264/AVC encoder. To minimize the hardware implementation cost, in this design we use only one unified architecture of 1D transform engine to perform all transform processes. While the performance of the design is improved by using a fast architecture of the multiplier in the quantizer. Furthermore, this architecture also enables to share the common part among multipliers that have the same multiplicand. The design has been implemented using FPGA technologies for prototyping purpose. Experimental results show that our architecture can completely finish transform and quantization processes of a 4:2:0 macroblock
in 228 clock cycles and the achieved performance is 115
MHz on a Virtex-II device (Xilinx) or 163 MHz on a Stratix-II device (Altera).
KW  - Integer Transform
KW  -  Quantization
KW  -  H.264/AVC Encoder
TI  - Low Cost and High Performance Implementation of Forward Transform and Quantization for an H.264/AVC Encoder
SP  - 231
M2  - Ho Chi Minh city
AV  - none
EP  - 236
T2  - The 1st Solid-State Systems Symposium (4S)
ER  -