TY  - CONF
ID  - SisLab57
UR  - https://eprints.uet.vnu.edu.vn/eprints/id/eprint/57/
A1  - Pham, Thi Hong
A1  - Pham, Phi Hung
A1  - Tran, Xuan Tu
A1  - Kim, Chulwoo
Y1  - 2008/06/04/
N2  - VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.
TI  - Analysis and Evaluation of Traffic-Performance in a Backtracked Routing Network-on-Chip
SP  - 13
M2  - Hoian, Vietnam
AV  - public
EP  - 17
T2  - The 2nd International Conference on Communications and Electronics (ICCE 2008)
ER  -