%A Thi Hong Pham
%A Phi Hung Pham
%A Xuan Tu Tran
%A Chulwoo Kim
%T Analysis and Evaluation of Traffic-Performance in a Backtracked Routing Network-on-Chip
%X VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.
%C Hoian, Vietnam
%D 2008
%P 13-17
%L SisLab57