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An Asynchronous Low-Power Innovative Network-on-Chip including Design-for-Test capabilities

Thonnart, Yvain and Tran, Xuan Tu and Vivet, Pascal and Beigne, Edith and Clermidy, Fabien and Durupt, Jean (2009) An Asynchronous Low-Power Innovative Network-on-Chip including Design-for-Test capabilities. In: 2009 International Conference on Advanced Technologies for Communications, Haiphong, Vietnam.

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The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot be satisfied only by point-to-point or shared-bus interconnects. By providing more bandwidth at reasonable power consumption, new communication infrastructures like NoCs seem promising, but are still limited by implementation issues. We present in this paper an Asynchronous Network-on-Chip architecture with two main innovations. Firstly, an automatic power regulation scheme is proposed to dynamically save leakage and dynamic power consumption. Secondly, due to the current lack of testing methodology for asynchronous logic, we propose a novel DfT solution to allow acceptance of the asynchronous NoC. The proposed architecture has been fully implemented in a STMicroelectronics CMOS 65nm technology, integrated in a complex test-chip and fabricated.

Item Type: Conference or Workshop Item (Paper)
Subjects: ?? AC ??
Electronics and Communications
?? Electronics ??
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Mr Duy-Hieu Bui
Date Deposited: 29 Jan 2010 09:42
Last Modified: 17 Jan 2017 02:39

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