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High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router

Le, Van Thanh Vu and Tran, Xuan Tu (2014) High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router. REV Journal on Electronics and Communications . pp. 68-74. ISSN 1859-387X

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In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port – named Routing Modification port – into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC/C++, simulated and verified within a 2D mesh 5x5 network platform. In normal communication mode, the static XY routing algorithm is used while the West-First algorithm with a proposed prohibited router surrounding technique will be applied in reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes as well as with the other works.

Item Type: Article
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 10 Jul 2015 14:06
Last Modified: 17 Jan 2017 02:14

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