Tran, Xuan Tu and Thonnart, Yvain and Durupt, Jean and Beroulle, Vincent and Robach, Chantal (2009) Design-for-Test Approach of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. IET Computers & Digital Techniques, 3 (5). pp. 487-500. ISSN 1751-8601
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Abstract
Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.
| Item Type: | Article |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering ISI-indexed journals |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Mr Duy-Hieu Bui |
| Date Deposited: | 26 Jan 2011 05:06 |
| Last Modified: | 17 Jan 2017 02:17 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/22 |
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