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A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration

Bui, Thanh Tung and Cheng, Xiaojin and Watanabe, Naoya and Kato, Fumiki and Kikuchi, Katsuya and Aoyagi, Masahiro (2016) A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration. In: 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016.

Full text not available from this repository.
Item Type: Conference or Workshop Item (Poster)
Subjects: Electronics and Communications
Divisions: Faculty of Electronics and Telecommunications (FET)
Depositing User: Bùi Thanh Tùng
Date Deposited: 28 Dec 2016 14:40
Last Modified: 28 Dec 2016 14:40
URI: http://eprints.uet.vnu.edu.vn/eprints/id/eprint/2326

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