Phan, Hai Phong and Tran, Xuan Tu and Yoneda, Tomohiro (2017) Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip. In: The 2017 IEEE International Conference on Integrated Circuit Design and Technology (IEEE ICICDT), 23-25 May 2017, Texas, USA.
Full text not available from this repository.Abstract
Dynamic Voltage and Frequency Scaling (DVFS) has been known as an efficient technique to reduce the power consumption of a Network-on-Chip (NoC). An important question in DVFS is how to change the voltage and frequency adaptable to the required performance of the system at run-time while reducing the power consumption as much as possible. Another problem is how a tool could quickly and efficiently validate or reject a NoC architecture employing DVFS. By integrating the Orion 2 power model, VNOC 2.0 simulator can be used as either a NoC simulation tool or a platform for implementing and investigating DVFS ideas. In this paper, we focus on developing a new solution for NoC architectures to save energy using fuzzy-logic algorithms. A controller is designed to predict the change of traffic load based on the fuzzy logic algorithm, then adjusts the voltage and frequency correspondingly to minimize the power consumption while keeping the performance of the whole system. An estimation of power consumption has been done by using VNOC 2.0 simulator. The simulation results show that our model can save up to 46% the power consumption of a 8x8 NoC.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 12 Apr 2017 01:56 |
| Last Modified: | 12 Apr 2017 01:56 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/2457 |
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