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Simulation and Performance Evaluation of a Network-on-Chip Architecture based on SystemC

Le-Van, Thanh Vu and Tran, Xuan Tu and Ngo, Dien Tap (2012) Simulation and Performance Evaluation of a Network-on-Chip Architecture based on SystemC. In: The 2012 International Conference on Advanced Technologies for Communications, 12-15 October 2012, Hanoi, Vietnam.

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The Network-on-Chip (NoC) paradigm has been recently known as a competitive on-chip communication solution for large complex systems such as multi-core and/or many-core systems thanks to its advantages. However, one of the main challenging issues for NoC design is that the network performance should be rapidly and early pre-proved for target applications. In this paper, we present a NoC simulation and evaluation platform allowing designers to simulate and evaluate the NoC performance with different network configuration parameters. The proposed platform has been implemented in SystemC to be easily modified to adapt different simulation strategies and to save the simulation time. With this platform, designers can deal with: (i) configuring the network topology, flow control mechanisms and routing algorithm; (ii) configuring various regular and application specific traffic patterns; and (iii) simulating and analyzing the network performance with the assigned traffic patterns in terms of latency and throughput. Obtained results with a 4x4 2D-mesh NoC architecture will be presented and discussed in this paper to demonstrate the proposed platform.

Item Type: Conference or Workshop Item (Paper)
Additional Information: ISBN: 978-1-4673-4350-3
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 01 Nov 2012 08:18
Last Modified: 17 Jan 2017 02:34

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