Nguyen, Ngo Doanh and Bui, Duy Hieu and Tran, Xuan Tu (2019) A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 11-14 November 2019, Bangkok.
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Abstract
Histogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 110kb SRAMs.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Key Laboratory for Smart Integrated Systems (SISLAB) Faculty of Electronics and Telecommunications (FET) |
| Depositing User: | Bùi Duy Hiếu |
| Date Deposited: | 06 Dec 2019 07:41 |
| Last Modified: | 06 Dec 2019 07:41 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/3723 |
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- A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. (deposited 06 Dec 2019 07:41) [Currently Displayed]
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