Le, Van Thanh Vu and Ngo, Dien Tap and Tran, Xuan Tu (2012) A SystemC based Simulation Platform for Network-on-Chip Architectures. In: 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), 13-15 August 2012, Danang, Vietnam.
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Abstract
As a promising solution for on-chip communication of large systems, the Network-on-Chip paradigm has been studied and developed by many research groups with different approaches. To bring the NoC paradigm into applications, designers have to prove their proposed NoC architectures through hardware description language (HDL) based simulations, or even through silicon test chip. Most of HDL based simulations have been implemented with low level HDLs, usually at register-transfer-level (RTL), requiring a huge amount of the simulation time. In this work, we propose a simulation platform modeled in SystemC to help designers to simulate their NoC designs with different parameters to meet the requirements of targeted applications. The proposed platform supports two-dimension topologies with a variable size of the network. The platform configuration, including platform parameters as well as communication patterns, is easily set by a shell bash. As a result, by using this platform, designers can simulate the network architecture and evaluate the network performance with a very short simulation time.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | ISBN: 978-4-88552-264-2 |
| Subjects: | Electronics and Communications ?? Electronics ?? Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 01 Nov 2012 08:31 |
| Last Modified: | 17 Jan 2017 02:35 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/40 |
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