Le, Van Thanh Vu and Phan, Hai Phong and Tran, Xuan Tu (2014) High-Level Modeling of a Novel Reconfigurable Network-on-Chip Router. In: The first NAFOSTED Conference on Information and Computer Science (NICS 2014), March 13-14, 2014, Hanoi.
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Abstract
This paper presents a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high level design using SystemC language. RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port -- named Routing Modification port -- into the conventional router architecture, the network router will be able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to meet the requirements of applications. The proposed architecture has been modeled in SystemC, simulated and verified within a 2D mesh 5x5 network platform. The static XY routing algorithm has been used in the normal communication mode while the West-First algorithm with a proposed prohibited router surrounding technique has been applied in the reconfiguration mode. Experimental results are also reported to compare the performance of the network architecture in different operation modes.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 26 Dec 2014 10:35 |
| Last Modified: | 17 Jan 2017 02:28 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/424 |
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