Vu, Tien Luan and Quach, Van Quy and Bui, Duy Hieu and Tran, Xuan Tu (2014) A Low-Cost Implementation of Advance Encryption Standard. In: The 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), 14-15 November 2014, Hanoi, Vietnam.
![[img]](https://eprints.uet.vnu.edu.vn/eprints/style/images/fileicons/application_pdf.png) |
PDF
Download (182kB) |
Abstract
The fast development of the Internet enables the information to be easily shared on a global network, however, it also raises the concerns about the secure of the information especially the sensitive data such as passwords, bank accounts, personal information and so on. One method to protect the sensitive data is using symmetric-key block cypher before and after sending it over the network using same secret key. Advanced Encryption Standard (AES) is currently considered as best symmetric-key block cipher. With the block size of 128-bits and the key length starting from 128-bit up to 256-bits, AES has been proved to takes years to break. However, AES implementations in software also require more computations and time to encrypt and decrypt the data. This bottleneck not only reduces the overall system throughput but also increases the power consumption especially in the embedded system, where there are limited computations and resources. To improve the throughput and reduce the power consumption of the AES crypto system, in this work, we proposed a combined, low-cost and high-throughput AES encryption and decryption architecture supporting all key-lengths as specified in the FIPS197. The design was modeled in VHDL and successfully synthesized using Xilinx Virtex 5 FPGA Chip 5VSX50TF with maximum frequency of 105 MHz and the maximum throughput of 300 Mbps.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 31 Dec 2014 05:29 |
| Last Modified: | 17 Jan 2017 02:24 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/431 |
Actions (login required)
 |
View Item |
