Nguyen, Kiem Hung and Tran, Quang Vinh and Tran, Xuan Tu (2014) Data Locality Exploitation for Coarse-grained Reconfigurable Architecture in Reconfigurable Network-on-Chips. In: The 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), 14-15 November 2014, Hanoi, Vietnam.
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Abstract
This paper proposes a Coarse-grained Reconfigurable Architecture (CGRA) applied to the multimedia processing and communications processing. To solve the huge bandwidth requirement of parallel processing arrays, the proposed CGRA architecture focuses on the exploitation of data locality to reduce data access bandwidth and increase efficiency of pipelined execution of the kernel loops. The proposed architecture has been modeled using both C and VHDL language aiming at simulating and analyzing various parameters of the target architecture, as well as supporting hardware/software co-verification when mapping applications onto the target system. Some benchmark applications have been mapped onto the models of the CGRA in order to prove the high flexibility and performance of the architecture that is suitable for a wide range of multimedia and communications processing applications. The proposed CGRA can be applied as computing resources in reconfigurable Network-on-Chips.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 31 Dec 2014 07:16 |
| Last Modified: | 17 Jan 2017 02:23 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/432 |
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