Nguyen, Thi Thuy and Tran, Xuan Tu (2014) A Novel Asynchronous First-In-First-Out Adapting to Multi-synchronous Network-on-Chips. In: The 7th International Conference on Advanced Technologies for Communications (ATC 2014), 15-17 October 2014, Hanoi, Vietnam.
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Abstract
The integration of a variety of IP cores into a single chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (GALS) approach addresses these challenges by dividing a chip into several independent subsystems working with different clock signals. In multi-synchronous Network-on-Chip (NoC) based on GALS architecture, the network routers run with different freq¬¬¬¬¬¬¬uencies, so the problem is how to transfer data safely and efficiently between them. In order to build a synchronization unit to tackle this problem, in this paper, we propose a novel efficient asynchronous First-In-First-Out architecture targeting to multi-synchronous NoCs. Token ring structure, register-based memory, and modified Asynchronous Assertion - Synchronous De-assertion techniques are applied to improve the performance of the proposed asynchronous FIFO. After simulating and verifying the design, we have implemented our asynchronous FIFO architecture with CMOS 180nm technology from AMS. Implementation results are analyzed and compared with previous works to show the strong points of our design.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 31 Dec 2014 07:41 |
| Last Modified: | 17 Jan 2017 02:25 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/434 |
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