Beigne, Edith and Fabien, Clermidy and Lhermet, Hélène and Miermont, Sylvain and Thonnart, Yvain and Tran, Xuan Tu and Valentian, Alexandre and Varreau, Didier and Vivet, Pascal and Popon, Xavier and Lebreton, Hugo (2009) An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE Journal of Solid State Circuits (JSSC), 44 (4). pp. 1167-1177.
|
PDF
Download (4MB) | Preview |
Abstract
In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.
| Item Type: | Article |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering ISI-indexed journals |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 02 Nov 2012 04:05 |
| Last Modified: | 17 Jan 2017 02:18 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/46 |
Actions (login required)
 |
View Item |
