Bui, Duy Hieu and Tran, Xuan Tu (2011) Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder. In: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), 8-10 August 2011, Hanoi, Vietnam.
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Abstract
Nowadays, System-on-Chip (SoC) systems are becoming more and more complex and need more time to model, simulate and verification. To reduce the complexity of the system and to boost development time, a new design methodology is required. Along with SystemC library, multi-level abstraction design methodology is proposed as the key concept in SoC design. In this paper, the authors apply this methodology to model and simulate a JPEG encoder using the combination of SystemC and VHDL to explore the architecture and implement the design into hardware components. Consequently, some parts of the JPEG encoder has successfully synthesized and implemented using FPGA tools. In conclusion, the design methodology gives designers a fast way and step-by-step to explore the hardware architecture, simulate and implement the system.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | ISBN: 978-4-88552-258-1 |
| Uncontrolled Keywords: | SystemC, VHDL, co-design, co-simulation, JPEG encoder |
| Subjects: | Electronics and Communications ?? Electronics ?? Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 02 Nov 2012 06:06 |
| Last Modified: | 17 Jan 2017 02:36 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/47 |
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