Items where Division is "Key Laboratory for Smart Integrated Systems (SISLAB)" and Year is 2017

A

Abdallah, Abderazek Ben and Dang, Nam Khanh and Okuyama, Yuichi (2017) A Low-overhead Fault tolerant Technique for TSV-based Interconnects in 3D-IC Systems. In: Sciences and Techniques of Automatic Control and Computer Engineering (STA), 2017 18th International Conference on, 21-23 December 2017, Monastir, Tunisia.

B

Belleville, Marc and Molnos, Anca and Sicard, Gilles and Christmann, Jean Frederic and Morche, Dominique and Bui, Duy Hieu and Puschini, Diego and Lesecq, Suzanne and Beigne, Edith (2017) Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. Journal of Low Power Electronics, 13 (3). pp. 298-309. ISSN 1546-1998

Bui, Duy Hieu and Puschini, Diego and Bacles-Min, Simone and Beigne, Edith and Tran, Xuan Tu (2017) AES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (12). pp. 3281-3290. ISSN 1063-8210

D

Dang, Nam Khanh and Ahmed, Akram Ben and Okuyama, Yuichi and Abdallah, Abderazek Ben (2017) Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems. IEEE Transactions on Emerging Topics in Computing . ISSN 2168-6750

Dang, Nam Khanh and Ahmed, Akram Ben and Tran, Xuan Tu and Okuyama, Yuichi and Abdallah, Abderazek Ben (2017) A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (11). pp. 3099-3112. ISSN 1063-8210

Dinh, Van Nam and Nguyen, Kiem Hung and Pham, Minh Trien and Tran, Xuan Tu (2017) An IDPSO Algorithm-based Application Mapping Method for Network-on-Chips. In: The 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 5-6 October 2017, Hanoi, Vietnam.

H

Ho, Huy Hung and Nguyen, Ngoc Sinh and Bui, Duy Hieu and Tran, Xuan Tu (2017) Accurate and Low Complex Cell Histogram Generation by Bypass the Gradient of Pixel Computation. In: The 4th NAFOSTED Conference on Information and Computer Science (NICS), 24-25 November 2017, Hanoi, Vietnam.

L

Le, Van Thanh Vu (2017) Reconfigurable Network-on-Chip Solution for Complex Systems. PhD thesis, VNU University of Engineering and Technology.

N

Nguyen, Kiem Hung and Le, Van Thanh Vu and Tran, Xuan Tu (2017) A Survey on Reconfigurable System-on-Chips. REV Journal on Electronics and Communications . ISSN 1859-387X

Nguyen, Kiem Hung and Phan, Thi Minh (2017) RTL Design of a Dynamically Reconfigurable Cell Array for Multimedia Processing. In: The 4th Nafosted Foundation for Science and Technology Development NAFOSTED Conference on Information and Computer Science (NICS), 24-25 November 2017, Hanoi, Vietnam. (In Press)

Nguyen, Quang Linh and Tran, Dinh Lam and Bui, Duy Hieu and Mai, Duc Tho and Tran, Xuan Tu (2017) Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing. In: The 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 5-6 October 2017, Hanoi, Vietnam.

P

Phan, Hai Phong and Tran, Xuan Tu and Yoneda, Tomohiro (2017) Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip. In: The 2017 IEEE International Conference on Integrated Circuit Design and Technology (IEEE ICICDT), 23-25 May 2017, Texas, USA.

T

Tran, Xuan Tu and Nguyen, Tung and Phan, Hai Phong and Bui, Duy Hieu (2017) ​AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100-A (8). pp. 1650-1660. ISSN 1745-1337

Tran, Xuan Tu and Phan, Xuan Hieu and Tran, Duc Tan and Pham, Manh Thang and Pham, Duc Thang and Pham, Bao Son (2017) Annual Scientific Report 2017 (ASR 2017). VNU-UET, Hanoi, Vietnam.