Dang, Nam Khanh and Tran, Xuan Tu and Merigot, Alain (2014) An Efficient Hardware Architecture for Inter-Prediction in H. 264/AVC Encoders. In: The 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, April 23-25, 2014, Warsaw, Poland.
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Abstract
In this paper, we propose a design methodology for the inter-prediction in H.264/AVC codecs by addressing the relationship between its main processes. The target of this methodology is to optimize the design in order to get better performance while keeping a reasonable design cost. An efficient hardware architecture for the inter-prediction in H.264/AVC codecs is then proposed with three key techniques: a modified full search algorithm with bandwidth efficiency, pipelining technique, and data reuse strategy. With this approach, the inter-prediction has been successfully designed and implemented with a CMOS 180nm technology which provides low cost in terms of latency, hardware overhead and memory bandwidth. The design is initially targeted to CIF video format; however, it is obviously suitable for real-time HD 1080p video format.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 26 Dec 2014 07:32 |
| Last Modified: | 17 Jan 2017 02:27 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/421 |
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