Design-for-Test of Asynchronous Networks-on-Chip

Tran, Xuan Tu and Beroulle, Vincent and Durupt, Jean and Robach, Chantal and Bertrand, François (2006) Design-for-Test of Asynchronous Networks-on-Chip. In: The 9th IEEE Symposium on Design and Diagnostics of Electronics Circuits and Systems (DDECS'06), 2006, Prague, Czech.

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Abstract

Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system-on-chip (SoC) designers. Some asynchronous Networks-on-Chip (NoCs) architectures are proposed for the communication within SoCs, but lack methodology and support for manufacturing test to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DfT architecture that allows to test the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC-based SoCs. This asynchronous DfT architecture is implemented in Quasi Delay Insensitive (QDI) asynchronous circuits and uses an area of about 20*8 KGates in an asynchronous NoC-based SoC of 4.5 MGates without memories.

Item Type:	Conference or Workshop Item (Paper)
Depositing User:	Mr Duy-Hieu Bui
Date Deposited:	11 May 2011 04:24
Last Modified:	17 Jan 2017 02:46
URI:	http://eprints.uet.vnu.edu.vn/eprints/id/eprint/27

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