Nguyen, Quang Linh and Tran, Dinh Lam and Bui, Duy Hieu and Mai, Duc Tho and Tran, Xuan Tu (2017) Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing. In: The 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 5-6 October 2017, Hanoi, Vietnam.
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Abstract
The increasing amount of digital video with supreme quality requires more efficient compression. As the complexity of video coding algorithm is rising, there are more demands for hardware accelerators and customized hardware. Context-based Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coding method adopted in the latest video compression standard, High Efficiency Video Coding (HEVC). Binary Arithmetic Encoder (BAE) is an essential component in CABAC, where the compression process happens. Because of the high data dependency and sequential coding characteristic, it is challenging to parallelize BAE. In this work, we proposed a low-cost and high-throughput hardware architecture for one core of BAE in HEVC. Our 4-stage pipelined BAE architecture is capable of processing one regular bin and up to 4 bypass bins per clock cycle with 30% reduction in terms of area when compared with the designs for one-core CABAC architecture. The design can compress an average of 1.4 bins per cycle. It achieves a throughput of 1 Gbin/s at the maximum operating frequency of 810 MHz with the area of 2.2 kGEs and the power consumption of 2.0 mW in Nangate 45nm technology.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 08 Dec 2017 03:27 |
| Last Modified: | 08 Dec 2017 03:27 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/2745 |
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