VNU-UET Repository

An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs

Tran, Xuan Tu and Tran, Van Huan (2011) An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs. REV Journal on Electronics and Communications , 1 (2). pp. 122-129. ISSN 1859-387X

PDF (JEC article) - Published Version
Download (458kB) | Preview
Official URL:


Thanks to many novel coding tools, H.264/AVC has become the most efficient video compression standard providing much better performance than previous standards. However, this standard comes with an extraordinary computational complexity and a huge memory access requirement, which make the hardware architecture design much more difficult and costly, especially for real-time applications. In the framework of H.264 codec hardware architecture project, this paper presents an efficient architecture of Forward Transform and Quantization (FTQ) for H.264/AVC codecs in mobile applications. To reduce the hardware implementation overhead, the proposed design uses only one unified architecture of 1-D transform engine to perform all required transform processes, including discrete cosine transform and Walsh Hadamard transform. This design also enables to share the common parts among multipliers that have the same multiplicands. The performance of the design is taken into consideration and improved by using a fast architecture of the multiplier in the quantizer, the most critical component in the design. Experimental results show that our architecture can completely finish transform and quantization processes for a 4:2:0 macroblock in 228 clock cycles and the achieved throughput is 445Msamples/s at 250MHz operating frequency while the area overhead is very small, 147755um2 (approximate 15KGates), with the 130nm TSMC CMOS technology.

Item Type: Article
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 20 Feb 2012 05:07
Last Modified: 17 Jan 2017 02:15

Actions (login required)

View Item View Item