Dang, Nam Khanh and Abdallah, Abderazek Ben (2018) Architecture and Design Methodology for Highly-Reliable TSV-NoC Systems. In: Horizons in Computer Science Research. Nova Science Publishers, pp. 199-246. ISBN 978-1-53613-327-1
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Abstract
During the past few decades, a lot of research has been focusing on Three-dimensional Networks-on-Chips (3D-NoCs) as an auspicious solution to alleviate the interconnect bottleneck and reduce the power consumption in current System-on-Chips (SoCs) designs. However, 3D-NoC systems are becoming susceptible to a variety of faults caused by crosstalk, radiation, oxide breakdown, and so on. As a result, a simple failure in a single transistor caused by one of these factors may compromise the entire system reliability where the failure can be illustrated in corrupted message delivery, time requirement unsatisfactory, or even sometimes the whole system collapse. This chapter presents a detailed faults/defects analysis and an efficient reliability assessment method to approximate the lifetime reliability of a NoC system. Also, this chapter presents an architecture and hardware design of a fault-tolerant TSV based 3D-NoC system which can handle major failures (i.e., hard-faults, soft-errors and TSV-defects) that can occur in TSV-based 3D-NoC systems.
| Item Type: | Book Section |
|---|---|
| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Khanh N. Dang |
| Date Deposited: | 18 Jun 2018 07:59 |
| Last Modified: | 18 Jun 2018 07:59 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/3006 |
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- Architecture and Design Methodology for Highly-Reliable TSV-NoC Systems. (deposited 18 Jun 2018 07:59) [Currently Displayed]
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