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Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication

Dang, Nam Khanh and Tran, Xuan Tu (2018) Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication. In: 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 12-14 September 2018, Hanoi, Vietnam.

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Soft errors are expecting to be accelerated with the shrinking of feature sizes due to low operating voltages and high circuit density. However, soft error rates per single-bit is expectedly reduced with technology scaling. With tight requirements for the area and energy consumption, using a low complexity and high coding rate error correction code (ECC) to handle soft errors in on-chip communication is necessary. In this work, we use Parity Product Code (PPC) and propose several supporting mechanisms to detect and correct soft errors. First, PPC can work as a parity check to detect single event upset (SEU) inside each flit. Then, to reduce the needed retransmission, a Razor flip-flop with parity check (RFF-w-P) is proposed to work with PPC. Since PPC can act like forward error correction (FEC), we also present a selective transmission in bit-indexes by using a transposable FIFO. Therefore, the proposed mechanism not only guarantee single error detection/correction but also provide 2+ error correction as FEC. The proposed work also reduce the area cost of FIFO in comparison to traditional coding methods and adapt too multiple error rates.

Item Type: Conference or Workshop Item (Paper)
Subjects: Electronics and Communications
Electronics and Communications > Electronics and Computer Engineering
Divisions: Faculty of Electronics and Telecommunications (FET)
Key Laboratory for Smart Integrated Systems (SISLAB)
Depositing User: Prof. Xuan-Tu Tran
Date Deposited: 13 Sep 2018 03:45
Last Modified: 13 Sep 2018 03:45

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