Univ of Aizu, Aizu Laboratory Inc (2019) ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置 TSV Error Tolerant Router Device for 3D Network On Chip. JP2019092020A.
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Abstract
A TSV error tolerant router device for 3D network-on-chip is disclosed. In a TSV error tolerant router device for a 3D network-on-chip having a plurality of routers arranged in each of a plurality of layers, and routers between the layers are connected by through-silicon vias, the through-silicon vias are provided. Each of which belongs to one corresponding router, has a plurality of clusters around the corresponding router, and is adjacent to the corresponding router when one of the plurality of clusters belonging to the corresponding router is defective A router is selected, and one cluster of the selected router is replaced in place of the defective cluster, maintaining connectivity between the layers. [Selection] Figure 2
| Item Type: | Patent |
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| Subjects: | Electronics and Communications Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Khanh N. Dang |
| Date Deposited: | 02 Aug 2020 06:21 |
| Last Modified: | 02 Aug 2020 06:21 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/4044 |
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