Dang, Nam Khanh and Le, Van Thanh Vu and Tran, Xuan Tu (2011) FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture. In: The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), 8-10 August 2011, Hanoi, Vietnam.
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Abstract
The Network-on-Chip (NoC) paradigm has recently been known as a promising solution for designing large complex Systems-on-Chip (SoCs), especially when the semiconductor technology turns into 3D integration era. This paper presents the design of a NoC router architecture which provides low latency, high throughput communication. The NoC router architecture is implemented on a Xilinx technology FPGA chip for prototyping purpose with an obtained latency of 8.1ns and a maximum throughput of 123Mflits/s on each communication channel. These results can be improved when the design is implemented with ASIC design flows.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | ISBN: 978-4-88552-258-1 |
| Uncontrolled Keywords: | Network-on-Chip |
| Subjects: | Electronics and Communications ?? Electronics ?? Electronics and Communications > Electronics and Computer Engineering |
| Divisions: | Faculty of Electronics and Telecommunications (FET) Key Laboratory for Smart Integrated Systems (SISLAB) |
| Depositing User: | Prof. Xuan-Tu Tran |
| Date Deposited: | 02 Nov 2012 06:10 |
| Last Modified: | 17 Jan 2017 02:35 |
| URI: | http://eprints.uet.vnu.edu.vn/eprints/id/eprint/48 |
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